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june 2015 docid028036 rev 1 1 / 15 this is information on a product in full production. www.st.com STD30N6LF6AG automotive - grade n - channel 60 v, 19 m typ., 24 a stripfet? f6 power mosfet in a dpak package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STD30N6LF6AG 60 v 25 m 24 a 40 w ? designed for automotive applications and aec - q101 qualified ? very low on - resistance ? very low gate charge ? high avalanche ruggedness ? low gate drive power loss applications ? switching applications description this device is an n - channel power mosfet developed using the stripfet? f6 technology with a new trench gate structure. the resulting power mosfet exhibits very low r ds(on) in all packages. table 1: device summary order code marking package packing STD30N6LF6AG 30n6lf6 dpak tape and reel am01475v1_ t ab d(2, tab) g(1) s(3)
contents STD30N6LF6AG 2 / 15 docid028036 rev 1 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 dpak (to - 252) type a package information ..................................... 9 4.2 dpak (to - 252) packing information ............................................... 12 5 revision hist ory ............................................................................ 14
STD30N6LF6AG electrical ratings docid028036 rev 1 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 60 v v gs gate - source voltage 20 v i d drain current (continuous) at t case = 25 c 24 a drain current (continuous) at t case = 100 c 17 i dm ( 1 ) drain current (pulsed) 96 a p tot total dissipation at t case = 25 c 40 w e as ( 2 ) single pulse avalanche energy 130 mj t stg storage temperature - 55 to 175 c t j operating junction temperature notes: (1) pulse width is limited by safe operating area. (2) starting t j = 25 c, i d = 24 a, v dd = 43.5 v. table 3: thermal data symbol parameter value unit r thj -case thermal resistance junction - case 3.75 c/w r thj -pcb (1) thermal resistance junction - pcb 35 notes: (1) when mounted on a 1- inch 2 fr - 4 board, 2 oz cu .
electrical characteristics STD30N6LF6AG 4 / 15 docid028036 rev 1 2 electrical characteristics (t case = 25 c unless otherwise specified) table 4: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 250 a 60 v i dss zero gate voltage drain current v gs = 0 v, v ds = 60 v 1 a v gs = 0 v, v ds = 60 v, t case = 125 c 100 i gss gate - body leakage current v ds = 0 v, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 2.5 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 12 a 19 25 m v gs = 4.5 v, i d = 12 a 24 30 table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 v - 1320 - pf c oss output capacitance - 88.5 - c rss reverse transfer capacitance - 58 - q g total gate charge v dd = 30 v, i d = 24 a, v gs = 10 v (see figure 14: "gate charge test circuit" ) - 26 - nc q gs gate - source charge - 6 - q gd gate - drain charge - 3.3 - table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 30 v, i d = 12 a, r g = 4.7 , v gs = 10 v (see figure 13: "switching times test circuit for resistive load" and figure 18: "switching time waveform" ) - 10 - ns t r rise time - 19 - t d(off) turn - off delay time - 56 - t f fall time - 7 -
STD30N6LF6AG electrical characteristics docid028036 rev 1 5 / 15 table 7: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source- drain current - 24 a i sdm (1) source- drain current (pulsed) - 96 a v sd (2) forward on voltage v gs = 0 v, i sd = 24 a - 1.3 v t rr reverse recovery time i sd = 24 a, di/dt = 100 a/s, v dd = 48 v, t j = 1 50 c (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 22.4 ns q rr reverse recovery charge - 22.2 nc i rrm reverse recovery current - 2 a notes: (1) current is limited by package. (2) pulse test: pulse duration = 300 s, duty cycle 1.5%.
electrical charact eristics STD30N6LF6AG 6 / 15 docid028036 rev 1 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STD30N6LF6AG electrical characteristics docid028036 rev 1 7 / 15 figure 8 : capacitance variations figure 9 : normalized gate thresho ld voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteri stics
test circuits STD30N6LF6AG 8 / 15 docid028036 rev 1 3 test circuits figure 13 : switching times test circuit for resistive load figure 14 : gate charge test circuit figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : switching time waveform
STD30N6LF6AG package information docid028036 rev 1 9 / 15 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 dpak (to - 252) type a package information figure 19 : dpak (to - 252) type a package outline
package information STD30N6LF6AG 10 / 15 docid028036 rev 1 table 8: dpak (to - 252) type a mechanical data dim. mm min. typ. max. a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d 6.00 6.20 d1 4.95 5.10 5.25 e 6.40 6.60 e1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 h 9.35 10.10 l 1.00 1.50 (l1) 2.60 2.80 3.00 l2 0.65 0.80 0.95 l4 0.60 1.00 r 0.20 v2 0 8
STD30N6LF6AG package i nformation docid028036 rev 1 11 / 15 figure 20 : dpak (to - 252) recommended footprint (dimensions are in mm)
package information STD30N6LF6AG 12 / 15 docid028036 rev 1 4.2 dpak (to - 252) packing information figure 21 : dpak (to - 252) tape outline p1 a0 d1 p0 f w e d b0 k0 t us er direction of feed p2 10 pi t ches cumul a ti ve t ole r an c e on tape +/- 0.2 mm us er direction of feed r bending radius b1 f or machine ref . only including d raf t and r adii c on centr ic a r ound b0 a m08852v1 top cover tape
STD30N6LF6AG package information docid028036 rev 1 13 / 15 figure 22 : dpak (to - 252) reel outline table 9: dpak (to - 252) tape and reel mechanical data tape reel dim. mm dim. mm min. max. min. max. a0 6.8 7 a 330 b0 10.4 10.6 b 1.5 b1 12.1 c 12.8 13.2 d 1.5 1.6 d 20.2 d1 1.5 g 16.4 18.4 e 1.65 1.85 n 50 f 7.4 7.6 t 22.4 k0 2.55 2.75 p0 3.9 4.1 base qty. 2500 p1 7.9 8.1 bulk qty. 2500 p2 1.9 2.1 r 40 t 0.25 0.35 w 15.7 16.3 a d b fu ll r ad ius tape slot in core for ta pe start 2.5mm min.width g measured at hu b c n 40mm min. access hole at s lot location t am06038v1
revision history STD30N6LF6AG 14 / 15 docid028036 rev 1 5 revision history table 10: document revision history date revision changes 30- jun - 2015 1 first release.
STD30N6LF6AG docid028036 rev 1 15 / 15 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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